1. Technical Field
The present invention relates to a semiconductor memory, and more particularly, to an apparatus for controlling on-die termination of a semiconductor memory and method of controlling the same.
2. Related Art
In general, when signals that are transmitted through a bus line having a predetermined impedance value meet a bus line having a different impedance value, some of the signals are lost. On-die termination (hereinafter, simply referred to as “ODT”) refers to the reduction of the signal loss through impedance matching of the two bus lines.
In general, the ODT can be controlled according to logical levels of some addresses of EMRS (Extended Mode Register Set) code addresses. That is, an appropriate effective resistance value is generated by an ODT signal that responds to the logical levels of some addresses, such that an ODT operation can be controlled. The ODT operation is usually activated during a write operation. However, an ODT circuit unit is designed regardless of the write/read operation.
While the ODT circuit unit operates, a failure may occur during the write/read operation of a DRAM. However, it may be difficult to determine whether the failure during the ODT operation results from an erroneous operation of the ODT circuit unit or the write or read operation of the actual DRAM.
When a failure related to the ODT circuit actually occurs, the failure is rarely analyzed. The failure may work as a delay factor in the development of the semiconductor memory and may affect the time to market.